silicon wafer close up
Silicon Wafer

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For Silicon Wafer inquiries, search Rogue Valley Microdevices’ Silicon Wafer Inventory for Wafer Diameters, Wafer Grades, Wafer Types, Dopants, Orientation, Wafer thickness, Surface Polish, Wafer Resistivity, Wafer TTV (please specify), Bow/Warp (please specify). For custom requirements, please contact us directly. 

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What is a Silicon Wafer?

Author: Dr. Dilek Isik Akcakaya

Silicon wafers are thin slices of pure or doped Silicon cut from Silicon Ingots. Silicon wafer thicknesses range from a few millimeters to a few microns and can be tuned according to the application through thinning processes.

“Silicon (Si), a non-metallic chemical element in the carbon family. Silicon makes up 27.7% of Earth’s crust; it is the second most abundant element in the crust, being surpassed only by oxygen.”

  • Definition: Encyclopaedia Britannica

Where are Silicon Wafers used?

While we do not come across a silicon wafer in our daily lives, chips made with Si wafers are all around us, finding their places in the electronics we use such as smartphones, smartwatches, computers, tablets, gas sensors, and smart home sensors.

Another example is the complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) used in cameras (Figure 1). When the data is received by a CIS it rebuilds the data as a picture with multiple corrections and noise reduction.

The processing of CMOS cameras requires the use of silicon wafers for reproducibility and for their well-established manufacturing processes in MOS processes with great precision in the microscale. 

Silicon Wafers Types and Dimensions

Silicon wafers are produced in different varieties according to need:

  • Monocrystalline Silicon: (also called single crystal wafer) Is formed of one large single Si crystal. Silicon ingots are grown with either CZ or FZ technique. 
  • Polycrystalline Silicon: (also called poly wafer) Multicrystalline Si with large grains are oriented in different directions and separated by grain boundaries.
  • Epitaxial Silicon Wafers: (also called epi wafer) is a wafer of semiconducting material made by epitaxial growth. The epitaxial layer can be doped differently or with an opposite type of dopant for different applications. In general, epi-layers are 1-20µm thick.
  • Epitaxial Silicon Wafers with a Buried Layer: Buried layers function as etch stops and dielectrics. Both are an essential part of MOS transistors. A wafer containing a buried layer and an epitaxial layer on top, are used in creating CMOS, bipolar transistors, and more.
  • Premium Grade Silicon wafers: (also called Prime Grade Silicon Wafers) are used for production. They are required to be free of dust, particles, chemical heterogeneities, and polishing faults. “Prime” refers to the highest possible grade of a silicon wafer.
  • Test Grade Silicon Wafers: Used in process monitoring or testing. While Test Grade Silicon wafers have the same chemical characteristics and are enough for testing production, they may contain some defects such as minor polishing faults.
  • SOI wafers: A Silicon on Insulator wafer is a layered Silicon–Insulator–Silicon substrate. The oxide layer is used as an etch stop or a dielectric layer.
  • Solar Grade Silicon Wafers: Are produced by Siemens polysilicon process and they are Polycrystalline Silicon Wafers.
Wafer size (mm)Wafer size (inch)Typical ThicknessIn-Stock
300 mm12 inch775 μm
200 mm8 inch725 μm.
150 mm6 inch675 μmShop Online
 100 mm4 inch525 μmShop Online
 76 mm3 inch375 μmShop Online
51 mm2 inch275 μm
Table 1 Standard wafer sizes

Silicon Wafer Geometrical Considerations:

Silicon wafers are produced in circular shapes and have rounded edges (Figures 2 and 3). They also come with primary and secondary flats or notches.

Silicon wafer requirements by SEMI standards:

Wafer DimensionWafer DimensionPrimary flat lengthSecondary flat lengthPrimary flat orientation:
50 mm
15.9 ± 1.5 mm.8.0 ± 1.5 mm
and 90° ± 1° ccw to primary flat.
(01 T) plane ± 0.5°.
76 mm
22.2 ± 2.0 mm.11.2 ± 1.5 mm and 90° ± 1° ccw to primary flat(01 T) plane ± 0.5°.
100 mm
525 µm (20.5 mils)32.5 mm18.0 mm40 µm40 µm10 µm<110>
150 mm
675 um (26.3 mils)57.5 mm37.5 mm60 µm60 µm10 µm<110>
Table 2, Silicon Wafer Requirements

conventional wafer edge profiles
Figure 2, Conventional wafer edge profiles [3].

Figure 3

Common orientation flats for different wafer types and reference notch for 200 mm and larger wafers according to SEMI. Wafer specifications can differ from SEMI standards [3]. In the first, {111} wafer shows one flat in the one flat in the <110> direction.

For ease of handling and processing, the edges of Silicon wafers are rounded according to the SEMI M1-0307 standard, which prevents the chipping and cracking of the wafers [1], [3]. Dimensions of Silicon wafers are also standardized using the SEMI standards to allow for process transfer and repeatability among fabs and equipment. 

Silicon wafers are highly brittle. Most steps of the wafer manufacturing process act on the wafers. The brittleness of silicon wafers is a major concern for all semiconductor industries due to increasing costs when wafers are broken near their completion phases [4]. Rounded edges are known to reduce the high stress faced by wafers.

What Are Silicon Wafer Flats?

Flats typically indicate the doping type of the wafer (n- or p-type) and the orientation of the wafer {100} or {111}, however, today manufacturers produce wafers according to the customers’ needs and this information may in some cases be deceiving. 

Silicon wafer to product process

For Silicon Wafer inquiries, search our Silicon Wafer Inventory for Wafer Diameters, Wafer Grades, Wafer Types, Dopants, Orientation, Wafer thickness, Surface Polish, Wafer Resistivity, Wafer TTV (please specify), Bow/Warp (please specify). For custom requirements, please contact us. 

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  • [3] M. Tilli, “Chapter Five – Silicon Wafers: Preparation and Properties,” in Handbook of Silicon-Based MEMS Materials and Technologies, V. Lindroos, M. Tilli, A. Lehto, and T. Motooka, Eds. Boston: William Andrew Publishing, 2010, pp. 71–88.
  • [4] P.-Y. Chen, M.-H. Tsai, W.-K. Yeh, M.-H. Jing, and Y. Chang, “Relationship between wafer edge design and its ultimate mechanical strength,” Microelectron. Eng., vol. 87, no. 11, pp. 2065–2070, Nov. 2010, doi: 10.1016/j.mee.2009.12.083.
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